Why does PCB18 layer gold plating board need simulation analysis

　　Taking the PCB 18 layer gold plate as an example, this paper explores in depth the necessity of simulation analysis in high-speed and high-density PCB design. By analyzing the characteristics of the gold plating process and the electrical and signal integrity challenges faced by 18 layer boards, the key role of simulation in ensuring design reliability, optimizing costs, and accelerating product launch is elucidated.

　　1. Introduction

　　With the development of electronic devices towards high speed, high performance, and miniaturization, the complexity of PCB design has significantly increased. As the core carrier of communication equipment, servers, computing cards, and other products, the design of 18 layer boards faces severe challenges in signal integrity, power integrity, and electromagnetic compatibility. ENIG, as a surface treatment process, has excellent weldability and flatness, but it also introduces new electrical characteristic variables. In this context, simulation analysis has shifted from being "optional" to "essential" and has become a key step in ensuring a successful design.

　　2. Design challenges and simulation necessity of 18 layer gold plate

　　2.1 Complexity of Layered Structure and High Density Interconnection

　　18 layer boards typically consist of multiple signal layers, power layers, and ground layers, with a complex stacked structure. Simulation analysis (especially electromagnetic field simulation) can accurately model:

　　Transmission line effect: the propagation characteristics of microstrip lines and strip lines under high-speed signals.

　　Crosstalk analysis: Evaluate the coupling noise between adjacent signal lines and optimize the wiring spacing.

　　Via effect: Analyze via stubs, impedance discontinuities, and return paths to reduce signal reflections.

　　2.2 Requirements for high-speed signal integrity

　　When the signal rate reaches the Gbps level (such as PCIe 5.0, DDR5), any slight impedance mismatch can cause eye closure and an increase in bit error rate. Simulation can:

　　Pre layout wiring analysis: Determine the topology structure and termination scheme before physical design.

　　Timing verification: Ensure clock synchronization and meet the requirements for establishing/maintaining time.

　　Loss analysis: Quantify conductor loss (skin effect), dielectric loss (material Df value), and select appropriate sheet materials.

　　2.3 Power Integrity Challenge

　　The noise of the power distribution network (PDN) in multi-layer boards directly affects the stability of chip operation. Simulation capability:

　　Target impedance analysis: Calculate the PDN impedance from DC to high frequency and optimize the decoupling capacitor configuration.

　　Synchronous switch noise assessment: Analyze the ground bounce/power collapse caused by simultaneous switching of outputs (SSO).

　　Resonance mode recognition: detect power source formation cavity resonance to avoid noise amplification.

　　2.4 Electrical effects of gold plating process

　　Although ENIG provides a good pad surface, its characteristics need to be considered in simulation:

　　Surface roughness: The micro roughness of the gold layer and nickel layer will increase the conductor loss at high frequencies (skin effect intensifies), which needs to be corrected in the simulation model.

　　Interface impedance: The metal interface of gold nickel copper may introduce small impedance discontinuities, which need to be evaluated for extremely high speed signals (such as 56Gbps or above).

　　Welding interface reliability: Simulate thermal stress distribution to avoid welding cracks caused by CTE mismatch (although mainly in the mechanical category, electrical connections are unreliable).

　　2.5 Pre evaluation of Electromagnetic Compatibility

　　The 18 layer board has high integration, and its radiation emission and anti-interference capabilities must be pre evaluated. Simulation can:

　　Predicting radiated noise: identifying potential EMI hotspots, optimizing shielding and filtering designs.

　　Sensitivity analysis: Evaluate the immunity of key signal lines to external interference.

　　3. Specific application scenarios of simulation analysis

　　3.1 Pre design stage: Architecture and pre layout simulation

　　Stacking design: Determine the optimal stacking sequence, medium thickness, and balance cost and performance through simulation.

　　Material selection: Evaluate the impact of different core board and semi cured sheet materials on loss and phase stability.

　　Key network pre analysis: topology exploration of clock, differential pair, and high-speed bus.

　　3.2 Mid design phase: Wiring optimization and verification

　　Wiring constraint generation: Based on simulation results, formulate matching rules for line width, line spacing, and length.

　　3D full wave simulation: precise electromagnetic modeling of complex via structures and connector areas.

　　Collaborative simulation: Combining chip IBIS/AMI models for system level signal integrity verification.

　　3.3 Post design stage: approval and problem investigation

　　Design Rule Check (DRC): not only performs geometric DRC, but also electrical DRC (such as impedance continuity).

　　Post simulation verification: Extract actual wiring parameters (S-parameters, SPICE model) for performance confirmation.

　　Sensitivity and Monte Carlo analysis: Evaluate the impact of manufacturing tolerances (such as line width ± 10%, medium thickness variation) on performance and improve design robustness.

　　4. The core value brought by simulation

　　Reduce risks and costs: Identify and solve potential problems in advance to avoid multiple board making due to design defects (18 layer board making is costly and time-consuming).

　　Improving performance and reliability: Through quantitative optimization, the product achieves a good balance in signal quality, power consumption, heat dissipation, EMC, and other aspects.

　　Accelerate product launch: compress the iterative cycle of design verification modification to shorten the research and development cycle.

　　Knowledge accumulation and reuse: Simulation models and experience can be transformed into enterprise design standards, enhancing the overall design capabilities of the team.

　　5. Conclusion

　　For PCBs such as 18 layer gold-plated boards, their design involves a deep integration of electrical performance, physical implementation, and manufacturing processes. Simulation analysis provides a virtual prototype testing platform, allowing engineers to gain in-depth insights and optimize design behavior before manufacturing. Especially in the face of high-speed signals, complex power networks, and subtle impacts of chemical processes, systematic simulation has become an indispensable engineering tool to ensure the success of products and achieve performance goals. Integrating simulation deeply into the design process is the only way to address the severe challenges of current electronic products.

　　Suggestion: Enterprises should establish a complete simulation process that covers signal integrity, power integrity, and electromagnetic compatibility, and equip corresponding tools (such as HFSS, SIwave, ADS, etc.), while strengthening the training of engineers' simulation capabilities to fully leverage the strategic value of simulation in complex PCB design.