Sharing of considerations for double-sided PCB design of high-speed digital circuits

　　The design of high-speed digital circuit double-sided PCB should take into account signal integrity, power integrity, electromagnetic compatibility, and adapt to the requirements of double-sided mounting technology. The core is to solve the problems of reflection, crosstalk, EMI, etc. in high-frequency signal transmission. The specific precautions are as follows:

　　The stacked structure and impedance control double-sided PCB have no inner reference plane, and impedance matching needs to be optimized through reasonable layout and routing. The target impedance is usually 50 Ω (RF/high-speed signal line) or 90 Ω (differential pair). Priority should be given to using the equivalent structure of "signal layer ground layer": one side is used as the main signal layer, and the other side is extensively laid and connected to the signal layer at multiple points, replacing the inner ground plane to reduce signal radiation and crosstalk. The width of the wiring should be calculated based on the dielectric constant and thickness of the board. For example, for FR-4 board (ε r=4.2) with a board thickness of 1.6mm, the microstrip line width corresponding to a 50 Ω impedance is about 3.2mm, which needs to be accurately verified through impedance calculation software.

　　The wiring rules for high-speed signal lines (such as clock, DDR, LVDS, etc.) should be short, straight, and continuous, avoiding via holes, right angles, and branch wiring. When wiring on both sides, high-speed signals should be concentrated on the same side as much as possible to reduce cross face vias; If it is necessary to cross the surface, grounding vias should be drilled nearby on both sides of the via to form a "grounding protection ring" and suppress impedance transients and radiation caused by the via. Differential signal lines must be strictly of equal length and spacing, with a length difference controlled within 5ml, and run parallel throughout the entire process. Crossing or changing layers is prohibited. Differential pairs in double-sided PCBs are recommended to be placed on the same side to reduce interlayer coupling differences.

　　The key points of grounding and power supply design adopt a large-area grounding strategy, where the grounding copper sheets on both sides are interconnected through dense vias (spacing ≤ 200mil) to form a low impedance grounding network and reduce grounding loops. The power supply wiring should be short and wide, with priority given to using thicker wires (≥ 0.5mm) or copper foil to reduce power impedance; Connect the power pin to the nearest filtering capacitor, which should be close to the chip power pin, and connect the ground terminal to the ground via through a short path to reduce the decoupling loop area. Avoid laying power cables under high-speed signal lines to prevent power noise from coupling into the signal.

　　High speed chips (such as FPGA, CPU, high-speed transceiver) should be prioritized in the central area of the PCB to shorten the core signal transmission path according to the layout specifications of electronic components; High frequency devices such as clock sources and crystal oscillators need to be located close to the load chip and surrounded by grounded copper foil, maintaining a minimum distance of 5mm from other devices to suppress clock signal radiation. When using a double-sided layout, heavy and large components (such as connectors and power modules) are mounted on the front, while high-speed chips and small components are distributed on both sides to avoid back side components affecting signal layer heat dissipation and grounding continuity. The input/output interface devices should be placed as close as possible to the edge of the PCB to reduce the distance of signal transmission inside the board. At the same time, electrostatic discharge (ESD) devices should be installed at the interface, and the grounding terminal of the ESD device should be grounded nearby.

　　The design of through holes and solder pads for high-speed signal through holes requires lead-free solder pads and solder mask designs to avoid impedance changes caused by solder infiltration; The through-hole diameter should be as small as possible (such as 0.8mm outer diameter and 0.4mm inner diameter) to reduce parasitic capacitance and inductance. The number of via holes on double-sided PCB should be reasonably controlled, and excess via holes should be grounded to avoid becoming antenna radiation interference; High speed signal line via holes need to be designed in pairs (signal via holes+ground via holes) to reduce via parasitic effects. The design of solder pads must meet the packaging requirements of high-speed devices, such as BGA device solder pads that need to match the ball diameter size, and the solder pad and wire connection should use a gradual transition to avoid impedance changes.

　　Signal lines with different rates of crosstalk and EMI suppression measures need to be laid out separately. The distance between high-speed signal lines and low-speed signal lines should be ≥ 3 times the line width to reduce crosstalk; Sensitive signals (such as reset and clock) should be kept away from interference sources (such as power modules and relays). The grounding copper foil on both sides should cover more than 70% of the board area, and all areas without wiring should be paved to reduce signal reflection and radiation; Set up grounding rings at the edge of the PCB to enhance electromagnetic shielding effect. Avoid long-distance parallel wiring. If it cannot be avoided, a grounding isolation line can be installed between the two lines, and grounding vias should be drilled every 200mil to cut off the crosstalk coupling path.

　　Process compatibility design for double-sided PCBs requires reserved process edges and positioning holes. The positioning holes should avoid high-speed signal lines and grounding copper sheets to prevent affecting signal integrity; The layout of components on both sides should be evenly distributed to avoid PCB deformation caused by uneven weight during installation. The size of the solder pads needs to be adapted to the SMT process, and the back solder pads can be appropriately reduced (10% smaller than the front) to reduce solder overflow during secondary reflow soldering; The solder mask layer needs to cover the non pad area to prevent solder diffusion from causing short circuits. At the same time, the solder mask window needs to be precise to prevent covering the pad from affecting welding.

　　For very high-speed designs such as DDR4 and above, PCIe Gen3 and above, the performance bottleneck of double-sided boards will be very prominent. If conditions permit, upgrading to a 4-layer board (TOP-GND-POWER-BOTTOM) is a cost-effective option that can provide a qualitative leap. The dual panel design of high-speed circuits is a test of engineers' experience and skills.